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Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
Manage and build a world class team managing ASIC design, micro-arch, SDC constraints and integration efforts of the project.Translate high level goals to measurable plans and milestones. Lead RTL design, quality checks, and manage schedule for on-time delivery of key IPs.Work with verification and physical design teams to achieve high quality design.Interface with IP teams and manage schedule and delivery of IPs for successful TO.Guide and mentor junior engineers as required.Hire and retain tier one engineers and foster teamwork with cross functional collaboration.Build a culture of execution excellence coupled with innovation.Build a team of hard-working and passionate leaders as we scale.Maintain close interactions with NPI, Packaging, DFT, Architecture teams.Own power, performance and area optimization of design.
Minimum Qualifications:
15+ years minimum of hands-on experience in ASIC design.MS in Electrical Engineering or Computer Science or equivalent industry experience.Demonstrable experience as a leader for large ASIC developments in advanced process nodes.Drive ASIC design methodology and flow from concept to release. Expert understanding of both FE and BE ASIC flows.
Preferred Qualifications
The candidate must have excellent analytical and problem-solving skills.Good communication skills to work effectively and optimally with different teams across Cisco.Experience using industry standard tools and adaptability to utilize home grown tools.Good understanding of Networking ASICs architecture.Understanding advanced power analysis and power integrity analysis.Knowledge of scripting languages Tcl, Python.Excellent English verbal and written communication skills.Understands the big picture and attention to detail during execution.Self-motivated, able to work in a highly cross functional team.
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